Active area bonding compatible high current structures

ABSTRACT

An integrated circuit with circuits under a bond pad. In one embodiment, the integrated circuit comprises a substrate, a top conductive layer, one or more intermediate conductive layers, layers of insulating material and devices. The top conductive layer has a at least one bonding pad and a sub-layer of relatively stiff material. The one or more intermediate conductive layers are formed between the top conductive layer and the substrate. The layers of insulating material separate the conductive layers. Moreover, one layer of the layers of insulating material is relatively hard and is located between the top conductive layer and an intermediate conductive layer closest to the top conductive layer. The devices are formed in the integrated circuit. In addition, at least the intermediate conductive layer closest to the top conductive layer is adapted for functional interconnections of select devices under the bond pad.

This application claims the benefit under 35 U.S.C. § 119(e) of U.S.Provisional Application Ser. No. 60/496,881, filed Aug. 21, 2003, andU.S. Provisional Application Ser. No. 60/507,539, filed Sep. 30, 2003,which are incorporated herein by reference (Attorney Docket No's125.090USPR and 125.090USP2, respectively).

TECHNICAL FIELD

The present invention relates generally to the formation ofsemiconductor devices and in particular a formation of active circuitsunder a bond pad.

BACKGROUND

Integrated circuits comprise two or more electronic devices formed inand/or on a substrate of semi-conductive material. Typically, theintegrated circuits include two or more metal layers that are used informing select devices and interconnects between said devices. The metallayers also provide electrical paths to input and output connections ofthe integrated circuit. Connections to the inputs and outputs of theintegrated circuit are made through bond pads. Bond pads are formed on atop metal layer of the integrated circuit. A bonding process (i.e. thebonding of a ball bond wire to the bond pad) can damage any activecircuitry formed under the metal layer upon which the bonding pad isformed. Therefore, present circuit layout rules either do not allow anycircuitry to be formed under the bonding pad or only allow limitedstructures that have to be carefully tested.

Damage under bonding pads can be caused by many reasons but mainly it isdue to the stresses which have occurred during bond wire attachmentprocess and the subsequent stresses after packaging. For example,temperature excursions after packaging exert both lateral and verticalforces on the overall structure. The metal layers of integrated circuitare typically made of soft aluminum that are separated from each otherby harder oxide layers. The soft aluminum tends to give under the forceswhile the harder oxide layers do not. This eventually leads to cracks inthe oxide layers. Once an oxide layer cracks, moisture can enter causingcorrosion of the aluminum layers and eventually failure of the circuitfunction. Therefore, the bonding process typically requires the realestate below the bond pad serve only as a buffer against damage thatoccurs during the bonding process. However, as chip designers try andreduce the size of chips it would be desired to able to use the realestate under the bonding pad for active circuits or interconnects.

For the reasons stated above and for other reasons stated below whichwill become apparent to those skilled in the art upon reading andunderstanding the present specification, there is a need in the art foran improved integrated circuit that effectively allows for use of thereal estate under bonding pads for active circuits and interconnects.

SUMMARY

The above-mentioned problems and other problems are resolved by thepresent invention and will be understood by reading and studying thefollowing specification.

In one embodiment, an integrated circuit is disclosed. The integratedcircuit comprises a substrate, a top conductive layer, one or moreintermediate conductive layers, layers of insulating material anddevices. The top conductive layer has a at least one bonding pad and asub-layer of relatively stiff material. The one or more intermediateconductive layers are formed between the top conductive layer and thesubstrate. The layers of insulating material separate the conductivelayers. Moreover, one layer of the layers of insulating material isrelatively hard and is located between the top conductive layer and anintermediate conductive layer closest to the top conductive layer. Thedevices are formed in the integrated circuit. In addition, at least theintermediate conductive layer closest to the top conductive layer isadapted for functional interconnections of select devices under the bondpad.

In another embodiment, an integrated circuit is disclosed. Theintegrated circuit comprises a substrate, device regions, a top metallayer, a second metal layer and a layer of relatively thick insulatingmaterial. The device regions are formed on and in the substrate. The topmetal layer has one or more bonding pads formed thereon. The deviceregions are located between the substrate and the top metal layer. Thesecond metal layer is located between the top metal layer and the deviceregions. The layer of relatively thick insulating material separates thetop metal layer from the second metal layer. The relatively thickinsulating layer is adapted to resist cracking.

In further another embodiment, another integrated circuit is disclosed.The integrated circuit includes a substrate, a plurality of devices, asecond metal layer and a first layer of insulating material. Theplurality of devices are formed on and in the substrate. The top metallayer has at least one bond pad formed on a surface of the top metallayer. A second metal layer is located between the top metal layer andthe substrate. Moreover, the second metal layer has gaps that areadapted to strengthen the integrated circuit. The first layer ofinsulating material is formed between the top metal layer and the secondmetal layer.

In another embodiment, a method of forming an integrated circuit withactive circuitry under a bond pad is disclosed. The method comprisesforming devices in and on a substrate. Forming a first metal layer.Forming a first layer of relatively thick insulating material overlayingthe first metal layer, wherein the thickness of the insulating materialstrengthens the integrated circuit. Forming a top metal layer overlayingthe relatively thick insulating material and forming a bond pad on asurface of the top layer.

In yet another embodiment, a method of forming an integrated circuit isdisclosed. The method comprises forming device regions is a substrate.Depositing a first metal layer overlaying the device regions. Patteringthe first metal layer to form gaps, wherein the gaps extend in a currentflow direction. Forming an insulating layer overlaying the first metallayer and filling in the gaps, wherein the gaps strengthen theintegrated circuit by providing pillars of harder insulating material.Depositing a top layer of metal overlaying the oxide layer and forming abond pad on a surface of the top layer of metal.

In still yet another embodiment, a method of forming an integratedcircuit is disclosed. The method comprises forming device regions in andon a substrate. Forming a first metal layer overlaying the deviceregions. Forming an insulating layer overlaying the first metal region.Forming a top metal layer overlaying the insulating layer including asub-layer of relatively stiff material near the oxide layer and forminga bonding pad on a surface of the top metal layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention can be more easily understood and furtheradvantages and uses thereof more readily apparent, when considered inview of the description of the preferred embodiments and the followingfigures in which:

FIG. 1 is a partial cross-sectional view of an integrated circuit of oneembodiment of the present invention;

FIG. 2 is a top view of a portion of a metal layer with gaps of oneembodiment of the present invention; and

FIGS. 3A through 3G are partial cross-sectional side views of one methodof forming an integrated circuit in one embodiment of the presentinvention.

In accordance with common practice, the various described features arenot drawn to scale but are drawn to emphasize specific features relevantto the present invention. Reference characters denote like elementsthroughout Figures and text.

DETAILED DESCRIPTION

In the following detailed description of the preferred embodiments,reference is made to the accompanying drawings, which form a parthereof, and in which is shown by way of illustration specific preferredembodiments in which the inventions may be practiced. These embodimentsare described in sufficient detail to enable those skilled in the art topractice the invention, and it is to be understood that otherembodiments may be utilized and that logical, mechanical and electricalchanges may be made without departing from the spirit and scope of thepresent invention. The following detailed description is, therefore, notto be taken in a limiting sense, and the scope of the present inventionis defined only by the claims and equivalents thereof.

In the following description, the term substrate is used to refergenerally to any structure on which integrated circuits are formed, andalso to such structures during various stages of integrated circuitfabrication. This term includes doped and undoped semiconductors,epitaxial layers of a semiconductor on a supporting semiconductor orinsulating material, combinations of such layers, as well as other suchstructures that are known in the art. Terms of relative position as usedin this application are defined based on a plane parallel to theconventional plane or working surface of a wafer or substrate,regardless of the orientation of the wafer or substrate. The term“horizontal plane” or “lateral plane” as used in this application isdefined as a plane parallel to the conventional plane or working surfaceof a wafer or substrate, regardless of the orientation of the wafer orsubstrate. The term “vertical” refers to a direction perpendicular tothe horizontal. Terms, such as “on”, “side” (as in “sidewall”),“higher”, “lower”, “over,” “top” and “under” are defined with respect tothe conventional plane or working surface being on the top surface ofthe wafer or substrate, regardless of the orientation of the wafer orsubstrate.

Embodiments of the present invention provide a method and structure ofan integrate circuit that allows the use of real estate under bondingpads for active devices and interconnects. Moreover, embodiments of thepresent invention provide a structure that can use all the metal layersbelow the bond pad for functional interconnections of the device. Inaddition, embodiments of the present invention also provide a structurethat allows submicron interconnects lines with a TiN top layer andrelatively wide lines capable of carrying high currents to existsimultaneously under a bond pad.

FIG. 1, illustrates a partial cross-section view of an integratedcircuit 100 of one embodiment of the present invention. In thisembodiment, the part of the integrated circuit 100 shown includes aN-channel MOS power device 102, a N-DMOS device 104 and a NPN bipolardevice 106. As FIG. 1 also illustrates three conductive layers, which inthis embodiment includes a first metal layer M1 108, a second metallayer M2 110 and a third metal layer M3 112. The metal layers 108, 110112 can be made of conductive material such as aluminum, copper and thelike. Moreover, in another embodiment, at least one of the metal layers108, 110 and is made by a sub-micron process that forms many sub-layersof alternating conductive layers. The third metal layer M3 112 can bereferred to as the top metal layer 112. As illustrated, a bond pad 130is formed on a surface of the third metal layer M3 112 by patterning apassivation layer 132. A ball bond wire 114 (bond wire 114) can becoupled to the bonding pad 130 to provide an input or output to theintegrated circuit 100. Although, this embodiment, only illustratesthree metal layers 108, 110 and 112, other embodiments have more or lessmetal layers. For example, in an embodiment with more than three metallayers, additional metal layers are formed between metal layers 108 and110. Each interconnect metal layer 108, 110 and 112 is formed byconventional methods known in the art such as depositing and patterning.

As illustrated in FIG. 1, vias 116 selectively couple the interconnectmetal layers 110 and 108 to form electrical connections between devices102, 104 and 106 of the integrated circuit 100. Further shown are vias118 that provide electrical connections to elements of the devices 102,104 and 106 and the first metal layer 108.

In one embodiment, the sub-micron process is used to form metal layer M2110 and metal layer M3 112. The sub-micron process uses many sub-layersto form a metal layer. In one embodiment, the sub-layers are alternatinglayers of Ti, TiN and Al alloys. Further in one embodiment, the toplayer of the sub-layers of metal layer 110 (i.e. the sub-layer facingmetal 112) is a TiN layer 120. The TiN layer 120 is used in thislocation because of its low reflective properties that aid in thepattering of metal layer 110. However, the presence of sub-layer 120tends to increase the probability that cracks will form in an oxidelayer separating the metal layer 110 from metal layer 112. Inparticular, because the TiN layer tends to be hard it doesn't yield whenstress is applied. As a result, lateral stresses on the separating oxidetend to form cracks in the separating oxide layer. Further in anotherembodiment, a layer of TiW forms sub-layer 120.

Embodiments, of the present invention reduce the probability of thecracks forming in the separating oxide layer 122. In one embodiment, theseparating oxide layer 122 (i.e. the oxide layer that separates metallayer 110 from metal layer 112) is formed to be relatively thick. In oneembodiment, the separating oxide layer 122 is formed to be at least 1.5um thick. The use of a separating oxide layer 122 that is relativelythick reduces the probabilities of crack forming in the oxide layer 122.In further another embodiment, the separating oxide layer is generally adielectric or insulating layer.

Moreover in one embodiment, the third metal layer M3 112 includes arelatively hard sub layer 126 of very stiff and hard material. The hardsub-layer 126 is formed adjacent the separating oxide layer 122 andopposite a side of the third metal layer M3 forming the bond pad 114.The hard sub layer 126 is very stiff and hard compared to aluminum. Thehard sub layer distributes lateral and vertical stresses over a largerarea of the oxide 122 thereby reducing the propensity of cracking in theoxide 122. In one embodiment, the material used for the hard sub-layer126 is TiN. This is due to the compatibility of TiN with conventionalsub-micron deposition and etch techniques. In yet another embodiment,the hard sub-layer 126 is a layer of nitride. In one embodiment, thehard sub-layer 126 is approximately 80 nm in thickness. In further otherembodiments, materials such as TiW are used for the hard sub-layer 126.

In further another embodiment, the second metal layer M2 110 is formedto have gaps 124 in selected areas. Very wide (lateral widths) of thesecond metal layer 110 tend to weaken the structure thus creating ahigher chance that cracks will occur in the separating oxide layer 122.In this embodiment, the gaps 124 tend to strengthen the structure byproviding pillars of harder oxide. The impact of the gaps 124 on thefunction of the integrated circuit is minimized by the proper layout.That is, the density of the gaps may be minimized so that a layoutdesign is not constrained significantly. In one embodiment, the gaps 124take no more than 10% of the total area of the second metal layer M2 110under the bond pads. In another embodiment, the gaps are oriented suchthat the impact on current flow through the second metal layer M2 110 isminimized. An example of gaps 124 formed to minimize the impact on thecurrent flow in the second metal layer M2 is illustrated in FIG. 2. FIG.2, also illustrates the third metal layer 112.

FIGS. 3A through 3G illustrates the forming of relevant aspects of oneembodiment of the present invention. FIG. 3A illustrates a partialcross-sectional side view of the start of the formation of an integratedcircuit 300 on a substrate 301. The partial cross-sectional side viewillustrates that integrated circuit 300 in this embodiment includes aN-Channel MOS 302, a N-DMOS 304 and a NPN device 306. It will beunderstood in the art that other types of devices can be formed in theintegrated circuit 300 and that the present invention is not limited toonly integrated circuits with N-Channel MOS, a N-DMOS and NPN devices.Since the formation of the devices 302, 304 and 306 are not a criticalpart of the present invention, FIG. 3A illustrates that they are alreadyformed. These devices 302, 304 and 306 are formed by techniques known inthe art such as deposition, etching masking and implantation. A firstinsulating layer 308 is formed overlaying devices 302, 304 and 306. Inone embodiment, the insulating layer 308 is a layer of first oxide layer308. Vias 310 are formed by techniques known in the art such as maskingand etching. The vias 310 are then filled with conductive material toform contacts with the first metal layer 312 and elements of the devices302, 304 and 306. The first metal layer 312 is formed by firstdepositing a metal layer and then patterning the first metal layer 312to form select interconnects. A second insulating layer 314 is thenformed overlaying the first metal layer M1 312 and exposed areas of thefirst oxide layer 308. In one embodiment, the second insulting layer 314is a second oxide layer 314. Vias are formed in the second layer ofoxide 314 by masking a surface of the second layer of oxide and etchingthe vias 316 down to select portions of the patterned first metal layer312. The vias 316 are then filled with conductive material.

Referring to FIG. 3B, a second metal layer M2 318 is deposited on asurface of the second oxide layer. In one embodiment, the second metallayer 318 is formed by a sub-micron process comprising a plurality ofalternating layers of different metals. In one embodiment, thealternating layers of metal are Ti, TiN and Al alloys. A top sub layer320 of the second metal layer M2 318 is made of TiN which aids in thepattering of the second metal layer M2 318. The top sub layer 320 isillustrated in FIG. 3C. As illustrated in FIG. 3C, in this embodiment,the second metal layer 318 is then patterned to form gaps 322. The gaps322 strengthen the structure by providing pillars of hard oxide. A thirdinsulating layer 324 is then formed overlaying the second metal layerM2. This is illustrated in FIG. 3D. In one embodiment, the thirdinsulating layer 324 is a third oxide layer 324. The third oxide layer324 also fills in the gaps 322. In one embodiment, the third oxide layer324 (separating oxide layer 324) is formed to be relatively thick.Moreover, in one embodiment the thickness of the separating oxide layer324 is at least 1.5 um.

A layer of relatively stiff and hard metal layer 326 is then formed onthe surface of the separating oxide layer 324. This is illustrated inFIG. 3E. This hard layer 326 distributes both lateral and verticalstress is over a larger area of the separating oxide layer 324. Someembodiments of the hard layer 326 are formed by a layer of nitride suchas TiN or SiN. In yet another embodiment the hard layer 326 is formed bya layer of TiW. Moreover, in one embodiment, the hard layer 326 isformed to be approximately 80 nm in thickness. Referring to FIG. 3F thethird metal layer M3 328 is formed overlaying hard layer 326. In oneembodiment, the hard layer 326 is a sub layer formed during theformation of the third metal layer M3 328 by conventional sub-microndeposition and etch techniques. In still another embodiment (not shown),the hard layer 326 is a sub layer of the third metal layer M3 328 formednear the separating oxide layer 324. A bond pad 330 is then formed on anupper surface of the third metal layer M3 328 by patterning a depositedpassivation layer 332. This is illustrated in FIG. 3G. Further asillustrated in FIG. 3G, a ball bond wire 334 is then coupled to the bondpad 330. Although, not shown in the Figures, vias are formed in therelatively thick oxide 324 so that the top metal layer 328 can also beused to interconnect devices. Moreover, it will be understood in the artthat a single integrated circuit may have multiple bond pads and thepresent invention is not limited to a single bond pad.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement, which is calculated to achieve the same purpose,may be substituted for the specific embodiment shown. This applicationis intended to cover any adaptations or variations of the presentinvention. Therefore, it is manifestly intended that this invention belimited only by the claims and the equivalents thereof.

1. An integrated circuit comprising: a substrate; a top conductivelayer, the top conductive layer having at least one bonding pad and asub-layer of relatively stiff material; one or more intermediateconductive layers formed between the top conductive layer and thesubstrate; layers of insulating material separating the conductivelayers from each other, one layer of the layers of insulating materialis relatively hard and is located between the top conductive layer andan intermediate conductive layer closest to the top conductive layer;and devices formed in the integrated circuit, wherein at least theintermediate conductive layer closest to the top conductive layer isadapted for functional interconnections of select devices under the bondpad.
 2. The integrated circuit of claim 1, wherein the sub-layer is madeof TiN.
 3. The integrated circuit of claim 1, wherein the sub-layer ismade of TiW.
 4. The integrated circuit of claim 1, where the sub-layeris a layer of nitride.
 5. The integrated circuit of claim 1, wherein thedevices are relatively high current devices and the one or moreintermediate conductive layers are formed into relatively wideinterconnect lines to accommodate relatively high currents.
 6. Theintegrated circuit of claim 1, wherein at least one of the conductivelayers further comprises: conductive sub-layers formed by a sub-micronprocess.
 7. The integrated circuit of claim 1, wherein the conductivelayers are metal layers.
 8. The integrated circuit of claim 7, whereinat least one of the metal layers are formed from a metal layer from agroup of metal layers comprising aluminum and copper.
 9. The integratedcircuit of claim 1, wherein the one or more intermediate conductivelayers further comprises: a second conductive layer, the secondconductive layer separated from the top conductive layer by a relativelythick insulating layer.
 10. The integrated circuit of claim 9, whereinthe relatively thick insulating layer is an oxide layer that is at least1.5 μm thick.
 11. The integrated circuit of claim 9, wherein the secondconductive layer further comprises: a layer of TiN positioned adjacentthe relatively thick insulation layer.
 12. The integrated circuit ofclaim 9, wherein the second conductive layer has gaps.
 13. Theintegrated circuit of claim 12 wherein the gaps take up no more than 10%of the total area of the second metal layer under the at least one bondpad.
 14. The integrated circuit of claim 12, wherein the gaps areorientated to minimize the impact on current flow through the secondmetal layer.
 15. An integrated circuit comprising: a substrate; deviceregions formed on and in the substrate; a top metal layer, the top metallayer having one or more bonding pads formed thereon, the device regionslocated between the substrate and the top metal layer; a second metallayer located between the top metal layer and the device regions; and alayer of relatively thick insulating material separating the top metallayer from the second metal layer, wherein the relatively thickinsulating layer is adapted to resist cracking.
 16. The integratedcircuit of claim 15, wherein the relatively thick insulating layer is alayer of oxide having a thickness of at least 1.5 μm.
 17. The integratedcircuit of claim 15, further including: one or more intermediate metallayers located between the device regions and the second metal layer.18. The integrated circuit of claim 15, wherein the second metal layerincludes a sub-layer of TiN located adjacent the layer of relativelythick insulating material.
 19. The integrated circuit of claim 15,wherein the second metal layer has gaps adapted to strengthen theintegrated circuit.
 20. The integrated circuit of claim 19, wherein thegaps take up no more than 10% of the total area of the second metallayer under the one or more bonding pads.
 21. The integrated circuit ofclaim 19, wherein the gaps are orientated to minimize the impact oncurrent flow through the second metal line.
 22. The integrated circuitof claim 15, further comprising: a layer of relatively stiff materialadapted to distribute both lateral and vertical stresses over a largerarea of the relatively thick insulating layer.
 23. The integratedcircuit of claim 22, wherein the layer of relatively stiff material isformed adjacent the top metal layer and the relatively thick insulatinglayer.
 24. The integrated circuit of claim 22, wherein the layer ofrelatively stiff material is made of TiN.
 25. The integrated circuit ofclaim 22, wherein the layer of relatively stiff material is made of TiW.26. The integrated circuit of claim 22, wherein the thickness of therelatively stiff material is approximately 80 nm.
 27. The integratedcircuit of claim 22, wherein the layer of relatively stiff material is alayer of nitride.
 28. The integrated circuit of claim 22, wherein thelayer of relatively stiff material is a sub-layer of the top metal layerformed by a sub-micron process.
 29. The integrated circuit of claim 28,wherein the sub-layer of relatively stiff material is formed near therelatively thick insulating layer.
 30. An integrated circuit comprising:a substrate; a plurality of devices formed on and in the substrate; atop metal layer having at least one bond pad formed on a surface of thetop metal layer; a second metal layer located between the top metallayer and the substrate, the second metal layer having gaps adapted tostrengthen the integrated circuit; and a first layer of insulatingmaterial formed between the top metal layer and the second metal layer.31. The integrated circuit of claim 30, wherein the density of the gapsin the second metal layer is minimized to minimize the impact on thefunction of the integrated circuit.
 32. The integrated circuit of claim30, wherein the gaps take up no more than 10% of the total area of thesecond metal line under an associated bond pad.
 33. The integratedcircuit of claim 30, wherein the gaps extend in a direction of a currentflow.
 34. The integrated circuit of claim 30, wherein the top metallayer includes a relatively stiff sub-layer located adjacent the firstinsulating layer.
 35. The integrated circuit of claim 30, wherein thesecond metal layer includes a TiN sub-layer located adjacent the firstinsulating layer.
 36. The integrated circuit of claim 30, wherein thesecond metal layer includes a TiW sub-layer located adjacent the firstinsulating layer.
 37. The integrated circuit of claim 30, wherein thefirst insulating layer is relatively thick.
 38. The integrated circuitof claim 37, wherein the first insulating layer is a first oxide layerhaving a thickness of at least 1.5 μm.
 39. A method of forming anintegrated circuit with circuitry under a bond pad, the methodcomprising: forming devices in and on a substrate; forming a first metallayer; forming a first layer of relatively thick insulating materialoverlaying the first metal layer, wherein the thickness of the firstinsulating layer strengthens the integrated circuit; forming a top metallayer overlaying the relatively thick insulating layer; and forming abond pad on a surface of the top layer.
 40. The method of claim 39,wherein the first layer of relatively thick insulating material is alayer of oxide having a thickness of at least 1.5 μm thick.
 41. Themethod of claim 39, further comprising; forming one or more intermediatemetal layers between the devices and the first metal layer.
 42. Themethod of claim 39, wherein forming the first metal layer furthercomprises: patterning the first metal layer to form gaps.
 43. The methodof claim 42, wherein the gaps take up no more than 10% of the total areaof the first metal layer under the bond pad.
 44. The method of claim 42,wherein the gaps are formed to be oriented such that the impact on thecurrent flow through the first metal layer is minimized.
 45. The methodof claim 42, wherein the gaps are formed to extend in a direction of acurrent flow in the first metal layer.
 46. The method of claim 39,wherein forming the top metal layer, further comprises: forming asub-layer of relatively stiff material.
 47. The method of claim 46,wherein the relatively stiff material TiN.
 48. The method of claim 46,wherein the relatively stiff material is made from a layer of nitride.49. The method of claim 46, wherein the relatively stiff material isformed near the first layer of relatively thick insulating material. 50.A method of forming an integrated circuit, the method comprising;forming device regions in a substrate; depositing a first metal layeroverlaying the device regions; pattering the first metal layer to formgaps, wherein the gaps extend in a current flow direction; forming aninsulating layer overlaying the first metal layer and filling in thegaps, wherein the gaps strengthen the integrated circuit by providingpillars of harder insulating material; depositing a top layer of metaloverlaying the insulating layer; and forming a bond pad on a surface ofthe top layer of metal.
 51. The method of claim 50, wherein theinsulating layer is a layer of oxide that is at least 1.5 μm thick. 52.The method of claim 50, wherein the gaps in the first metal layer takeup no more than 10% of the total area of the metal line under the bondpad.
 53. The method of claim 50, wherein forming the top metal layerfurther comprises: forming a sub-layer of relatively stiff materialadjacent the insulating layer.
 54. The method of claim 53, wherein therelatively stiff material is TiN.
 55. The method of claim 53, whereinthe relatively stiff material is TiW.
 56. The method of claim 53,wherein the relatively stiff material is made from a sub-layer ofnitride.
 57. A method of forming an integrated circuit, the methodcomprising: forming device regions in and on a substrate; forming afirst metal layer overlaying the device regions; forming an insulatinglayer overlaying the first metal region; forming a top metal layeroverlaying the insulating layer including a sub-layer of relativelystiff material near the insulating layer; and forming a bonding pad on asurface of the top metal layer.
 58. The method of claim 57, wherein thesub-layer of relatively thick material is TiN.
 59. The method of claim57, wherein the relatively stiff material is TiW.
 60. The method ofclaim 57, wherein the sub-layer of the relatively thick material isformed from a layer of nitride.
 61. The method of claim 57, wherein theinsulating layer is an oxide layer having thickness of not less than 1.5μm.
 62. The method of claim 57, wherein forming the first metal layerfurther comprises: patterning the first metal layer to form gaps,wherein the gaps take up no more than 10% of a total layer area of thefirst metal layer under the bond pads.
 63. The method of claim 57,further comprising: forming one or more intermediate metal layersbetween the first metal layer and the device regions; and patterning theone or more intermediate metal layers to form interconnects between thedevices.
 64. The integrated circuit of claim 14, wherein the gaps beingorientated to minimize the impact on the current flow through the secondmetal layer, further comprises: extending the gaps in the direction ofthe current flow.
 65. The integrated circuit of claim 21, wherein thegaps being orientated to minimize the impact on the current flow throughthe second metal layer, further comprises: extending the gaps in thedirection of the current flow.
 66. The method of claim 39, whereinforming devices in and on a substrate includes forming at least one ofthe devices under the bond pad.
 67. The method of claim 50, wherein thebond pad is formed directly over at least one of the device regions. 68.An integrated circuit comprising: a substrate; a top conductive layer,the top conductive layer having at least one bonding pad and at leastone sub-layer wherein the at least one sub-layer is relatively morestiff than the other sub-layers of the top conductive layer; one or moreintermediate conductive layers formed between the top conductive layerand the substrate; one or more layers of insulating material separatingthe one or more conductive layers from each other; and devices formed inthe integrated circuit, wherein at least the intermediate conductivelayer closest to the top conductive layer is adapted for functionalinterconnections of select devices under the bond pad.
 69. Theintegrated circuit of claim 68, wherein the at least one sub-layer isone from a group comprising TiN, SiN and TiW.
 70. The integrated circuitof claim 68, wherein at least one of the intermediate conductive layershas gaps.
 71. The integrated circuit of claim 70, wherein the gapsextend in a direction of current flow to minimize their impact oncurrent flow.
 72. The integrated circuit of claim 68, wherein the atleast one of the intermediate conductive layers is the intermediateconductive layer closest the top conductive layer.
 73. The integratedcircuit of claim 68, wherein one layer of the layers of insulatingmaterial is thicker than the other layers of insulating material and islocated between the top conductive layer and an intermediate conductivelayer closest to the top conductive layer.
 74. An integrated circuitcomprising: a substrate; device regions formed on and in the substrate;a top metal layer, the top metal layer having one or more bonding padsformed thereon, the device regions located between the substrate and thetop metal layer; a second metal layer located between the top metallayer and the device regions; and a first layer of insulating materialseparating the top metal layer from the second metal layer, wherein theinsulating layer has a thickness selected to resist cracking.
 75. Theintegrated circuit of claim 74, wherein the layer of insulating materialis at least 1.5 μm thick.
 76. The integrated circuit of claim 74,wherein the second metal layer has one or more gaps extending in thedirection of current flow.
 77. The integrated circuit of claim 74,further comprising: a plurality of intermediate metal layers between thetop metal layer and the substrate, the plurality of metal layersincluding the second metal layer; and layers of insulating materialseparating the conductive layers from each other, the layers ofinsulating material including the first layer of insulating material.78. The integrated circuit of claim 77, wherein the plurality ofintermediate conductive layers under the one or more bonding pads areadapted for active devices and functional interconnections.
 79. Anintegrate circuit comprising: a substrate; a top conductive layer, thetop conductive layer having at least one bonding pad formed thereon; oneor more intermediate conductive layers formed between the top conductivelayer and the substrate; one or more layers of insulating materialseparating the one or more conductive layers from each other; one of theone or more intermediate conductive layers closest the top conductivelayer having gaps adapted to strengthen the integrated circuit; anddevices formed in the integrated circuit, wherein the one or moreintermediate conductive layers are adapted for functionalinterconnections of select devices under the bond pad.
 80. Theintegrated circuit of claim 79, further comprising: a sub-layer ofrelatively stiff material that is stiffer than the top conductive layer,the sub-layer of relatively stiff material formed between the topconductive layer and one of the one or more layers of insulationmaterial separating the at least one intermediate conductive layerclosest to the top conductive layer.
 81. The integrated circuit of claim79, wherein one layer of the layers of insulating material is thickerthan the other layers of insulating material and is located between thetop conductive layer and an intermediate conductive layer closest to thetop conductive layer.
 82. The integrated circuit of claim 79, whereinthe gaps in the one of the one or more intermediate conductive layersclosest the top conductive layer extend in a direction of current flowto minimize their impact on current flow.
 83. The integrated circuit ofclaim 79, wherein the gaps in the one of the one or more intermediateconductive layers closest the top conductive layer take up no more than10% of the area under the at least one bonding pad.
 84. An integratedcircuit comprising: a substrate; a top conductive layer, the topconductive layer having at least one bonding pad formed thereon and atleast one sub-layer wherein the at least one sub-layer is relativelymore stiff than the remaining top conductive layer; one or moreintermediate conductive layers formed between the top conductive layerand the substrate, one of the one or more intermediate conductive layersclosest the top conductive layer having gaps adapted to strengthen theintegrated circuit; one or more layers of insulating material separatingthe one or more conductive layers from each other, the one or morelayers of insulating material including a first layer of insulatingmaterial separating the top metal layer from the closest one of the oneor more intermediate conductive layers, wherein the insulating layer hasa thickness selected to resist cracking; and devices formed in theintegrated circuit, wherein the one or more intermediate conductivelayers under the at least one bonding pad are adapted for active devicesand functional interconnections.
 85. A method of forming an integratedcircuit, the method comprising: forming devices on and in a substrate;forming one or more intermediate conductive layers overlaying thesubstrate; forming one or more layers of insulating material separatingthe one or more conductive layers from each other; forming a topconductive layer, the top conductive layer including at least onesub-layer of material that is relatively more stiff than the remainingtop conductive layer; and forming at least one bonding pad on the topconductive surface, wherein the at least one sub-layer of material thatis relatively stiff is adapted to prevent the cracking of the one ofmore intermediate conductive layers under the at least one bonding padso that one or more intermediate conductive layers under the at leastone bonding pad can be used for functional interconnections of selectedones of the devices.
 86. The method of claim 85, wherein the sub-layerthat is relatively stiff is made from one from a group of materialscomprising TiN, SiN and TiW.
 87. The method of claim 85, furthercomprising: forming one of the one or more layers of insulating materialbetween the top conductive layer and an intermediate conductive layerclosest the top conductive layer to be relatively thicker than theremaining one of more layers of insulation.
 88. The method of claim 85,further comprising: forming gaps an in one of the one or moreintermediate conductive layers to form pillars of relatively stiffinsulating material passing through the one of the one or moreintermediate conductive layers.
 89. The method of claim 88, wherein theone of the one or more intermediate conductive layers is theintermediate conductive layer closest the top conductive layer.
 90. Amethod of forming an integrated circuit, the method comprising: formingdevice regions on and in a substrate; forming a first metal layeroverlaying the substrate; forming a top metal layer overlaying the firstmetal layer; forming at least one bonding pad on the top metal layer;and forming a first layer of insulating material separating the topmetal layer from the first metal layer, wherein the first layer ofinsulating material has a thickness selected to resist cracking.
 91. Themethod of claim 90, wherein the first layer of insulating material isformed to be at least 1.51 μm thick.
 92. The method of claim 90, furthercomprising: forming one or more intermediate metal layers between thefirst metal layer and the substrate; and forming one or more insulationlayers to separate the one or more intermediate metal layers form eachother.
 93. The method of claim 90, further comprising; forming asub-layer of material between the top metal layer and the first layer ofinsulating material, the sub-layer of material being relatively morestiff than the remaining top metal layer such that stresses on the topmetal layer that occur during the formation of the one or more bondingpads are distributed over a larger area of the first layer of insulatingmaterial to reduce the probability of cracking the first layer ofinsulating material.
 94. The method of claim 90, further comprising:forming gaps in the first metal layer to form pillars of relativelystiff insulating material passing through the first metal layer.
 95. Amethod of forming an integrated circuit, the method comprising: formingdevices in and on a substrate; forming a top conductive layer overlayingthe substrate; forming at least one bonding pad on the top conductivelayer; forming one or more intermediate conductive layers between thetop conductive layer and the substrate; forming one or more layers ofinsulating material separating the one or more conductive layers fromeach other; and forming gaps in one of the one or more intermediateconductive layers closest the top conductive layer, the gaps beingadapted to prevent cracking of the one or more intermediate conductivelayers under the at least one bond pad by forming pillars of relativelystiff insulation material passing through the one of the one or moreintermediate conductive layers closest the top conductive layer, whereinthe one or more intermediate conductive layers are adapted forfunctional interconnections of select devices under the bond pad. 96.The method of claim 95, wherein the gaps in the one of the one or moreintermediate conductive layers closest the top conductive layer andformed in the direction of the current flow to reduce the effect of thegaps on the current flow.
 97. The method of claim 95, furthercomprising: forming a sub-layer of material between the top conductivelayer and one of the layers of insulating material separating the one ofthe one or more intermediate conductive layers closest the topconductive layer from the top conductive layer, the sub-layer ofmaterial being relatively more stiff than the remaining top conductivelayer such that stresses on the top conductive layer that occur duringthe formation of the at least one bonding pad are distributed over alarger area of the one or more layers of insulating material to reducethe probability of cracking the one or more layers of insulatingmaterial.
 98. The method of claim 95, further comprising: forming one ofthe one or more layers of insulating material between the top conductivelayer and an intermediate conductive layer closest the top conductivelayer to be relatively thicker than the remaining one of more layers ofinsulation.